High speed serial transceivers undergo bit error rate (BER) testing during characterization. The BER is the rate of occurrence of erroneous bits in data transmission or reception. This testing is performed using a BER analyzer, which can be located on-chip or off-chip.
An example of an off-chip BER analyzer 10 is now described with reference to FIG. 1A. The BER analyzer 10 includes a test data generator 12 and a BER analysis circuit 13. The device under test 16 includes a receiver 17 and a transmitter 18. A physical PHY receive channel 14 couples the test data generator 12 to the receiver 17, and a physical PHY transmit channel 15 couples the BER analysis circuit 13 to the transmitter 18.
The test data generator 12 generates a psuedo-random binary sequence for use as test data and transmits it to the device under test 16 over the PHY receive channel 14. The device under test 16 then transmits the test data back to the test apparatus 11, via the transmitter 18 and over the PHY transmit channel 15. The BER analysis circuit 13 receives the test data and determines the BER thereof by comparing the received test data to expected check data.
This off-chip BER analyzer 10 has a variety of drawbacks, however. For example, errors in the PHY receive channel 14 can affect the determined BER of the PHY receive channel 14. In addition, this off-chip BER analyzer 10 is unable to test a single channel protocol, such as USB 2.0. Furthermore, such off-chip BER analyzers 10 can be prohibitively costly. In addition, the BER testing of a variable burst-to-burst latency protocol (e.g. MIPI, MPHY, etc) with such off-chip BER analyzers 10 is not possible. In addition, in some cases, loopback between the PHY receive channel 14 and PHY transmit channel 15 may not be feasible, as these interfaces may not be pin to pin mapped.
The cost of an on-chip BER analyzer 20, such as that shown in FIG. 1B, may be less than that of an off-chip BER analyzer. Here, the device under test is an integrated circuit chip 22, and includes two separate and distinct physical channels, PHY1 23 and PHY2 25, that use different voltage levels and protocols in some cases. The channel PHY1 23 is coupled to a first BER analyzer circuit 24, while the channel PHY2 25 is coupled to a second BER analyzer circuit 26.
In operation, a test data generator 21 generates a psuedo-random binary sequence for use as test data and transmits it to the BER analyzer 20, over the channels PHY1 23 and PHY2 25, to BER analyzers 24 and 26. The BER analyzer circuits 24 and 26 determine the bit error rates of the channels PHY1 23 and PHY2 25.
As mentioned, this on-chip BER analyzer 20 is cheaper than an off-chip BER analyzer. However, it has drawbacks as well. For example, separate BER analyzer circuits 24 and 26 are needed for each channel PHY1 23 and PHY2 25. This means that this on-chip BER analyzer 20 increases the area overhead for applications in which multiple PHY channels are to be tested.
Consequently, further development in the area of bit error rate analyzers is needed.